Implementation Of No-Flow Underfills On Chip Scale Packages

With decreasing solder joint size, underfill is critical in meeting reliability standards of Chip Scale Package (CSP) technology. The potential for no-flow underfills in this area is enormous in that they can be incorporated into the standard SMT process without post reflow processing.

Download our white paper to learn more about the reliability of several commercial no-flow underfills when compared to CSPs assembled with and without underfills, and learn why no-flow underfill implementation on CSP increases reliability as compared to non-underfilled devices.

Processing And Reliability Of Flip Chip With Lead-Free Solders On Halogen-Free Microvia Substrates

Not only is the electronics industry looking to make smaller, lighter products, but also ones that are environmentally friendly. This white paper takes a look at flip chip assembly processes and reliability in the context of environmentally conscious aspects of manufacturing and high process throughput.

Download our white paper to learn more about implementing green, low cost flip chip material systems and processing in an effort to minimize environmental impact.

Download the white paper now.

Thermal Dissipation Analysis In Flip Chip On Board And Chip On Board Assemblies

There is increasing application of direct chip attach packaging technologies in electronics manufacturing. This white paper explores the thermal management of three direct chip attach technologies, including experimental measurements of junction-to-ambient thermal resistance and thermal dissipation paths for three interconnect technologies:

  • solder attach
  • anisotropic adhesive attach
  • isotropic adhesive attach

Download our white paper to learn more about the first order chip-scale thermal design model for flip chip assemblies that exhibits good agreement with experimental measurements.

Prediction Of Solder Interconnects Wetting And Experimental Evaluation

As the density of interconnects in electronics packaging increases and the size of microelectronic devices decreases, the formation of solder joints during the assembly process becomes increasingly important.

However, the failure to achieve interconnect yield due to poor solder wetting leads to increased costs in electronics manufacturing.

In this white paper, you’ll uncover how we developed a solder interconnect wetting dynamics model, including the impact of environmental temperature and geometry. You’ll also gain access to a new analysis methodology to predict solder interconnect wetting. Finally, you’ll receive solutions to address causes of poor wetting during electronics assembly in order to reduce design, development, and implementation time.

Download the white paper now.